Xilinx Vivado can be overwhelming for a logic designer who is creating their first design for a contemporary Xilinx device. This course describes the various design flows, including hdl only flow, block flow and a hybrid of block and hdl. Each flow includes a simulation options, and adding the Integrated Logic Analyzer to a design. We introduce the Vitis SDK to allow the logic designer to create simple test programs, and describe the AXI4-Lite bus which is the most common interface between processor and logic.
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Xilinx Vivado Essentials for the Logic Designer
Getting started with Vivado and the SDK
Table of contents
You will learn
✓ Getting started designing FPGAs with Xilinx Vivado Design Tools
• Working knowledge of either VHDL or Verilog
This course is for
• Beginning Xilinx FPGA Logic Designers
FPGA / ASIC Design Engineer
Twenty five years of experience in designing FPGAs and ASICs for the commercial and aerospace markets. Instructor for many years at California State University. Lecturer and instructor for major companies including Boeing, Rockwell, Intel, Xilinx, and AMD. FPGA designs in aerospace, communications, image processing, and automation. Popular lecturer for development seminars and company learning events.