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VSD – RTL Synthesis Q&A Webinar

Here are the answers, you were looking for....
3.6
3.6/5
(16 reviews)
454 students
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6.6

CourseMarks Score®

5.5

Freshness

6.4

Feedback

7.4

Content

Platform: Udemy
Video: 1h 37m
Language: English
Next start: On Demand

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CourseMarks Score®

6.6 / 10

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5.5 / 10
This course was last updated on 5/2018.

Course content can become outdated quite quickly. After analysing 71,530 courses, we found that the highest rated courses are updated every year. If a course has not been updated for more than 2 years, you should carefully evaluate the course before enrolling.

Student Feedback

6.4 / 10
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Content Score

7.4 / 10
Video Score: 7.8 / 10
The course includes 1h 37m video content. Courses with more videos usually have a higher average rating. We have found that the sweet spot is 16 hours of video, which is long enough to teach a topic comprehensively, but not overwhelming. Courses over 16 hours of video gets the maximum score.
The average video length is 3 hours 21 minutes of 22 VLSI courses on Udemy.
Detail Score: 9.0 / 10

The top online course contains a detailed description of the course, what you will learn and also a detailed description about the instructor.

Extra Content Score: 5.5 / 10

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Table of contents

Description

Welcome to first ever QnA webinar on RTL synthesis using Yosys. This webinar was conducted on 19th May, 2018 with Clifford Wolf
Its a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of Yosys which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Cliffordwill be answering 23 queries on RTL synthesis. TOP23 query submissions are directly eligible for certificates from our company VSD Corp. Pvt. Ltd.

Note of AppreciationI have worked with Clifford in my course on TCL programming Part 1& 2, and really Thank him for all his guidance for making of TCLprogramming course.
Clifford has more than 20+ years of experience and is been known the Architect and Father of Yosys, OpenSCAD (now maintained by Marius Kintel), SPL (a not very popular scripting language), EmbedVM (a very simple compiler+vm for 8 bit micros), Lib(X)SVF (a library to play SVF/XSVF files over JTAG), ROCK Linux (discontinued since 2010)
All the best and happy learning.

You will learn

✓ Students will get structured answers to queries which they might otherwise find difficult to search online
✓ Perception about synthesis and opensource tools will change
✓ Students and professionals from other fields will be excited to choose Synthesis as their full-time career as so many things are yet to explore

Requirements

• Knowledge of Yosys is nice to have, but not required
• Digital design knowledge is needed
• Knowledge of synthesis and physical design flow is essential

This course is for

• Anyone who wants to enter VLSI front-end design field should take this course, as this course will answer lot of questions related to synthesis in general
• Anyone looking to start using opensource tool Yosys for synthesis
• Anyone curious to know what’s happening in the world of RTL synthesis

How much does the VSD - RTL Synthesis Q&A Webinar course cost? Is it worth it?

The course costs $14.99. And currently there is a 82% discount on the original price of the course, which was $84.99. So you save $70 if you enroll the course now.
The average price is $12.9 of 22 VLSI courses on Udemy.

Does the VSD - RTL Synthesis Q&A Webinar course have a money back guarantee or refund policy?

YES, VSD – RTL Synthesis Q&A Webinar has a 30-day money back guarantee. The 30-day refund policy is designed to allow students to study without risk.

Are there any SCHOLARSHIPS for this course?

Currently we could not find a scholarship for the VSD - RTL Synthesis Q&A Webinar course, but there is a $70 discount from the original price ($84.99). So the current price is just $14.99.

Who is the instructor? Is Kunal Ghosh a SCAM or a TRUSTED instructor?

Kunal Ghosh has created 41 courses that got 10,860 reviews which are generally positive. Kunal Ghosh has taught 38,530 students and received a 4.2 average review out of 10,860 reviews. Depending on the information available, Kunal Ghosh is a TRUSTED instructor.
Digital and Sign-off expert at VLSI System Design(VSD)
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm’s Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.

Hands on with Technology @    

1) MSM (mobile station mode chips) – MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.   

2) Memory test chips – Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.   

3) DDR-PHY test chips – DDR-PHY test chips are basically tested for high speed data transfer   

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.   

5) “IR aware STA” and “Low power STA”   

6) Analyzed STA engine behavior for design size up to 850 million instance count   ACADEMIC    

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.    

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software  

PUBLICATION   

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”  

2) Concurrent + Distributed MMMC STA for ‘N’ views  

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit  

4) Placement-aware ECO Methodology – No Slacking on Slack  




Tips on order in which you need to learn VLSI and become a CHAMPION:

If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.

Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2  and Timing ECO webinar courses, respectively

Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.

And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course

All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle

Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor 

Connect with me for more guidance !!   

Hope you enjoy the session best of luck for future

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6.6

CourseMarks Score®

5.5

Freshness

6.4

Feedback

7.4

Content

Platform: Udemy
Video: 1h 37m
Language: English
Next start: On Demand

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