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VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130

How to configure ope-source compiler OpenRAM for 130nm technology node
4.2
4.2/5
(11 reviews)
124 students
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CourseMarks Score®

9.2

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7.9

Feedback

7.3

Content

Platform: Udemy
Video: 1h 13m
Language: English
Next start: On Demand

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CourseMarks Score®

8.3 / 10

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9.2 / 10
This course was last updated on 4/2021.

Course content can become outdated quite quickly. After analysing 71,530 courses, we found that the highest rated courses are updated every year. If a course has not been updated for more than 2 years, you should carefully evaluate the course before enrolling.

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7.9 / 10
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Content Score

7.3 / 10
Video Score: 7.7 / 10
The course includes 1h 13m video content. Courses with more videos usually have a higher average rating. We have found that the sweet spot is 16 hours of video, which is long enough to teach a topic comprehensively, but not overwhelming. Courses over 16 hours of video gets the maximum score.
The average video length is 3 hours 21 minutes of 22 VLSI courses on Udemy.
Detail Score: 8.6 / 10

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Table of contents

Description

This webinar aims at design of 1024×32 SRAM cell array (32Kbits or 4KB) with a configuration of 1.8 V operating voltage and access time less than 2.5ns using Google SkyWater SKY130 PDKs and OpenRAM memory compiler.
Static Random-Access Memory (SRAM) has become a standard element of any Application Specific Integrated Circuit (ASIC), System-On-Chip (SoC), or other micro-architectures. For this wide variety of applications, SRAMs are configured using parameters like the word-length, bit lines, operating voltage, access time, and most importantly the technology node. The access time of an SRAM cell is the time require for a read or write operation of SRAM.
Manually configuring the SRAM for every change in parameter seems a slightly in-efficient and tedious task. Due to this reason, the memory compiler is used on a large scale, as it facilitates easy configuration and optimization of memory. OpenRAM, an open-source memory compiler is used for characterization and generation of SRAM designs.
This webinar mentioned multiple open-source circuit schematic design, layout design, SPICE simulations tools and memory compiler. The tools used are explained in detail. All the Skywater SKY130 PDKs related files are added to the repository mentioned in webinar, which can be used without installing the complete PDKs. To install or get other details of Skywater PDKs, it can be found in Skywater official website

You will learn

✓ Configure open-source memory compiler OpenRAM for any memory size
✓ SRAM custom cell design
✓ Memory GDS/Lib/Lef file types

Requirements

• VSD – Custom Layout course on Udemy
• VSD – Circuit design and SPICE simulation course on Udemy
• VSD – Library characterization course on Udemy

This course is for

• VLSI Beginner who wants to quickly learn about various custom cells like 6T-SRAM, DFF
• VLSI professionals who want to know how to configure open-source memory compiler OpenRAM for custom memory IP generation

How much does the VSD Intern - OpenRAM configuration for 4kB SRAM using Sky130 course cost? Is it worth it?

The course costs $14.99. And currently there is a 82% discount on the original price of the course, which was $84.99. So you save $70 if you enroll the course now.
The average price is $12.9 of 22 VLSI courses on Udemy.

Does the VSD Intern - OpenRAM configuration for 4kB SRAM using Sky130 course have a money back guarantee or refund policy?

YES, VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130 has a 30-day money back guarantee. The 30-day refund policy is designed to allow students to study without risk.

Are there any SCHOLARSHIPS for this course?

Currently we could not find a scholarship for the VSD Intern - OpenRAM configuration for 4kB SRAM using Sky130 course, but there is a $70 discount from the original price ($84.99). So the current price is just $14.99.

Who is the instructor? Is Kunal Ghosh a SCAM or a TRUSTED instructor?

Kunal Ghosh has created 41 courses that got 10,860 reviews which are generally positive. Kunal Ghosh has taught 38,537 students and received a 4.2 average review out of 10,860 reviews. Depending on the information available, Kunal Ghosh is a TRUSTED instructor.
Digital and Sign-off expert at VLSI System Design(VSD)
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm’s Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.

Hands on with Technology @    

1) MSM (mobile station mode chips) – MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.   

2) Memory test chips – Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.   

3) DDR-PHY test chips – DDR-PHY test chips are basically tested for high speed data transfer   

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.   

5) “IR aware STA” and “Low power STA”   

6) Analyzed STA engine behavior for design size up to 850 million instance count   ACADEMIC    

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.    

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software  

PUBLICATION   

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”  

2) Concurrent + Distributed MMMC STA for ‘N’ views  

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit  

4) Placement-aware ECO Methodology – No Slacking on Slack  




Tips on order in which you need to learn VLSI and become a CHAMPION:

If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.

Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2  and Timing ECO webinar courses, respectively

Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.

And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course

All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle

Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor 

Connect with me for more guidance !!   

Hope you enjoy the session best of luck for future

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8.3

CourseMarks Score®

9.2

Freshness

7.9

Feedback

7.3

Content

Platform: Udemy
Video: 1h 13m
Language: English
Next start: On Demand

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