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VSD Intern – 10-bit DAC design using eSim and Sky130

Design 10-bit DAC from scratch using eSim - open source EDA tool for circuit design by FOSSEE IIT Bombay and Sky130 PDKs
(96 reviews)
716 students
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CourseMarks Score®







Platform: Udemy
Video: 1h 46m
Language: English
Next start: On Demand

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Detailed Analysis

CourseMarks Score®

8.5 / 10

CourseMarks Score® helps students to find the best classes. We aggregate 18 factors, including freshness, student feedback and content diversity.

Freshness Score

9.4 / 10
This course was last updated on 6/2021.

Course content can become outdated quite quickly. After analysing 71,530 courses, we found that the highest rated courses are updated every year. If a course has not been updated for more than 2 years, you should carefully evaluate the course before enrolling.

Student Feedback

8.2 / 10
We analyzed factors such as the rating (4.2/5) and the ratio between the number of reviews and the number of students, which is a great signal of student commitment.

New courses are hard to evaluate because there are no or just a few student ratings, but Student Feedback Score helps you find great courses even with fewer reviews.

Content Score

7.3 / 10
Video Score: 7.8 / 10
The course includes 1h 46m video content. Courses with more videos usually have a higher average rating. We have found that the sweet spot is 16 hours of video, which is long enough to teach a topic comprehensively, but not overwhelming. Courses over 16 hours of video gets the maximum score.
The average video length is 3 hours 21 minutes of 22 VLSI courses on Udemy.
Detail Score: 8.7 / 10

The top online course contains a detailed description of the course, what you will learn and also a detailed description about the instructor.

Extra Content Score: 5.5 / 10

Tests, exercises, articles and other resources help students to better understand and deepen their understanding of the topic.

This course contains:

0 article.
0 resource.
0 exercise.
0 test.

Table of contents


Most of the signals around us, in the world we live in are not digital in nature, rather they are analog. The digital systems can understand only digital signals, not analog. Hence, it becomes important to interface the digital systems we the external analog world. The analog input signals are to be converted to digital signals using Analog to Digital Converters at the input end of the digital system. After the processing by the system, the digital signals are to be converted back into analog signals using Digital to Analog Converters.
A n-bit Digital to Analog Converter (DAC) takes a n-bit digital word and converts it into a proportional analog voltage with respect to the reference voltage. The potentiometric DAC uses the concept of Voltage Divider. In an N-bit DAC, the analog voltage range, i.e. the Vref (here 3.3 V) is equally divided into 2^N voltage values. This is achieved by a series on 2^N equal resistors and taps are provided across each R. The combination of switches to tap the values is designed using the N-bit digital word as input.
This circuit was designed using eSim
eSim (previously known as Oscad / FreeEDA) is a free/libre and opensource EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using free/libre and opensource software such as KiCad, Ngspice and GHDL. eSim is released under GPL.
eSim offers similar capabilities and ease of use as any equivalent proprietary software for schematic creation, simulation and PCB design, without having to pay a huge amount of money to procure licenses. Hence it can be an affordable alternative to educational institutions and SMEs. It can serve as an alternative to commercially available/licensed software tools like OrCAD, Xpedition and HSPICE.

You will learn

✓ eSim tool usage and installation
✓ DAC IP design – hierarchical approach
✓ Basic circuit design using eSim and Sky130


• VSD – Circuit design and SPICE simulations
• VSD – Custom layout

This course is for

• Beginner VLSI students curious to know about eSim and circuit design
• Expert VLSI Physical designers curious to know about custom IP design using real foundry PDKs like Sky130

How much does the VSD Intern - 10-bit DAC design using eSim and Sky130 course cost? Is it worth it?

The course costs $14.99. And currently there is a 82% discount on the original price of the course, which was $84.99. So you save $70 if you enroll the course now.
The average price is $12.9 of 22 VLSI courses on Udemy.

Does the VSD Intern - 10-bit DAC design using eSim and Sky130 course have a money back guarantee or refund policy?

YES, VSD Intern – 10-bit DAC design using eSim and Sky130 has a 30-day money back guarantee. The 30-day refund policy is designed to allow students to study without risk.

Are there any SCHOLARSHIPS for this course?

Currently we could not find a scholarship for the VSD Intern - 10-bit DAC design using eSim and Sky130 course, but there is a $70 discount from the original price ($84.99). So the current price is just $14.99.

Who is the instructor? Is Kunal Ghosh a SCAM or a TRUSTED instructor?

Kunal Ghosh has created 41 courses that got 10,860 reviews which are generally positive. Kunal Ghosh has taught 38,537 students and received a 4.2 average review out of 10,860 reviews. Depending on the information available, Kunal Ghosh is a TRUSTED instructor.
Digital and Sign-off expert at VLSI System Design(VSD)
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm’s Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.

Hands on with Technology @    

1) MSM (mobile station mode chips) – MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.   

2) Memory test chips – Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.   

3) DDR-PHY test chips – DDR-PHY test chips are basically tested for high speed data transfer   

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.   

5) “IR aware STA” and “Low power STA”   

6) Analyzed STA engine behavior for design size up to 850 million instance count   ACADEMIC    

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.    

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software  


1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”  

2) Concurrent + Distributed MMMC STA for ‘N’ views  

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit  

4) Placement-aware ECO Methodology – No Slacking on Slack  

Tips on order in which you need to learn VLSI and become a CHAMPION:

If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.

Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2  and Timing ECO webinar courses, respectively

Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.

And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course

All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle

Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor 

Connect with me for more guidance !!   

Hope you enjoy the session best of luck for future

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CourseMarks Score®







Platform: Udemy
Video: 1h 46m
Language: English
Next start: On Demand

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