This course focuses on phase locked loops (PLL) theory and behavioral modeling. PLLs are one of the most important blocks in RF communication transceiver systems. PLL systems exist in variety of high frequency applications, from simple clock circuits, to local oscillators (LOs) for high performance radio communication links, and ultra-fast switching frequency synthesizers in vector network analyzers (VNA). This course explains different types of PLLs with detailed explanations on individual sub-blocks. It includes PLL design and calculations with lots of examples and homework. There are also system level simulations and behavioral design using Advanced Design System (ADS) software. Phase noise of PLL is discussed in this course using equations, systems analysis, and there are tutorials that guide you to simulate the behavioral phase noise model of PLL and observe the system impact on VCO phase noise. There are also discussion about fractional PLL concept and features in this course.
It is important to remind you that this course covers the behavioral analysis of PLL sub-blocks however, it does not include any transistor level simulation and this topic will be covered on different course which will be released by Rahsoft in the future.
Prerequisites and topics you need to be familiar with for this course are:
•Electronics and analog circuit design (intermediate level)
•Control Theory (basic level)
Concepts such as:
•open and closed Loop gain
•Open loop – close loop systems
•Basic op amp
•Please be advised that this course contains more math than previous courses.
•PLL system design requires an understanding of transfer function derivations and stability analysis which needs system calculations and involves university level mathematical calculations.