Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process. Explanations of the difference in sequential and concurrent VHDL. Discussions of good synchronous design methodology. Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.
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Introduction to VHDL for FPGA and ASIC design
From VHDL basics to sophisticated testbench coding
Table of contents
You will learn
✓ Practical FPGA and ASIC RTL design using VHDL
• Basic understanding of electronics and logic
This course is for
• Beginner FPGA or ASIC designer
FPGA / ASIC Design Engineer
Twenty five years of experience in designing FPGAs and ASICs for the commercial and aerospace markets. Instructor for many years at California State University. Lecturer and instructor for major companies including Boeing, Rockwell, Intel, Xilinx, and AMD. FPGA designs in aerospace, communications, image processing, and automation. Popular lecturer for development seminars and company learning events.