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Functional Verification – a holistic view

- comprehensive introduction to functional verification
4.8
4.8/5
(30 reviews)
226 students
Created by

9.0

CourseMarks Score®

9.5

Freshness

9.4

Feedback

7.5

Content

Platform: Udemy
Video: 1h 10m
Language: English
Next start: On Demand

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Detailed Analysis

CourseMarks Score®

9.0 / 10

CourseMarks Score® helps students to find the best classes. We aggregate 18 factors, including freshness, student feedback and content diversity.

Freshness Score

9.5 / 10
This course was last updated on 7/2021.

Course content can become outdated quite quickly. After analysing 71,530 courses, we found that the highest rated courses are updated every year. If a course has not been updated for more than 2 years, you should carefully evaluate the course before enrolling.

Student Feedback

9.4 / 10
We analyzed factors such as the rating (4.8/5) and the ratio between the number of reviews and the number of students, which is a great signal of student commitment.

New courses are hard to evaluate because there are no or just a few student ratings, but Student Feedback Score helps you find great courses even with fewer reviews.

Content Score

7.5 / 10
Video Score: 7.7 / 10
The course includes 1h 10m video content. Courses with more videos usually have a higher average rating. We have found that the sweet spot is 16 hours of video, which is long enough to teach a topic comprehensively, but not overwhelming. Courses over 16 hours of video gets the maximum score.
The average video length is 7 hours 33 minutes of 17 Verilog HDL Programming courses on Udemy.
Detail Score: 9.3 / 10

The top online course contains a detailed description of the course, what you will learn and also a detailed description about the instructor.

Extra Content Score: 5.5 / 10

Tests, exercises, articles and other resources help students to better understand and deepen their understanding of the topic.

This course contains:

0 article.
0 resource.
0 exercise.
0 test.

Table of contents

Description

Overview
Functional Verification is one of the most time-consuming processes in ASIC design cycle; yet a structured introductory course/training/education on this topic is often missing. Neither the educational institutes offer this nor there are vendors offering such training. While several language specific courses are offered by EDA vendors, a comprehensive training on fundamentals of functional verification is lacking. This course gives you an in-depth introduction to the different aspects of functional verification including different testbench architectures. This course covers all aspects of functional verification ranging from verification architecture to building testbenches, gate level simulation and various technologies used in verification such as simulation, formal, emulation.
Objectives
•To explore what is verification and why it is needed and how it is achieved.
•To examine the different testbench architectures available
•To suggest widely used guidelines and need for a methodology
•To elaborate on all the different terminologies, buzz words used in the industry
•To introduce different stages in functional verification such as RTL simulation, gate level simulation, emulation etc. and to address the challenges in each one of them
Table of Contents
Session 1: Introduction
•ASIC Design Flow
•Paradigm Shift
•Verification Challenge
•A quick Verification 101
Session 2: Different Verification Technologies
•Simulation based
•Formal methods
•Equivalence checking
•Model checking
•Theorem Proving
•Hybrid
•Emulation
•FPGA based
•Processor based
Session 3: Metric Driven Verification (MDV)
•Code Coverage
•Assertion coverage (Control Centric)
•Functional Coverage (Data centric)
Session 4: Writing Testbenches
•What is a testbench anyway?
•Basic testbenches
•Rudimentary
•TCL based
•HDL based – basic ones
Session 5: Coverage measurement in Verification
•What is coverage?
•Types of coverage
•Line Coverage
•Condition Coverage
•Toggle Coverage
•FSM Coverage
•Functional Coverage
Session 6: Gate Level Simulation (GLS) & SDF annotation
•What is Gate Level Simulation
•SDF Annotation – typical timing violations
Session 7: Regressions – keeping the design stable
•Need for regressions
•Verification management

Session 8: Tips & tricks, Best Known Methods (BKMs)
•Coding tips
•Methodology notes
•Summary

You will learn

✓ Functional Verification
✓ Why electronic designs require verificaiton
✓ Various technologies in Verification (Simulation, Formal Verification, Emulation)
✓ What is a TestBench (TB)
✓ Metric Driven Verification (MDV)

Requirements

• Verilog
• Digital Design

This course is for

• VLSI Design Verification engineers
• Students in EE/EC/CS streams with keen interest in VLSI domain

How much does the Functional Verification - a holistic view course cost? Is it worth it?

The course costs $14.99. And currently there is a 25% discount on the original price of the course, which was $19.99. So you save $5 if you enroll the course now.
The average price is $15.4 of 17 Verilog HDL Programming courses on Udemy.

Does the Functional Verification - a holistic view course have a money back guarantee or refund policy?

YES, Functional Verification – a holistic view has a 30-day money back guarantee. The 30-day refund policy is designed to allow students to study without risk.

Are there any SCHOLARSHIPS for this course?

Currently we could not find a scholarship for the Functional Verification - a holistic view course, but there is a $5 discount from the original price ($19.99). So the current price is just $14.99.

Who is the instructor? Is Srinivasan Venkataramanan a SCAM or a TRUSTED instructor?

Srinivasan Venkataramanan has created 7 courses that got 204 reviews which are generally positive. Srinivasan Venkataramanan has taught 4,061 students and received a 4.0 average review out of 204 reviews. Depending on the information available, Srinivasan Venkataramanan is a TRUSTED instructor.
CTO at CVC Pvt Ltd
Srini is a technology expert in the field of VLSI /Semiconductors and EDA. He has been in the forefront of VLSI front-end design & verification using SystemVerilog &  UVM. Srini has co-authored several books in this field including PSL, SVA, VMM, UVM and more. Srini has trained more than 15,000 working professionals across the globe on various topics such as SystemVerilog, OVM, VMM, UVM, SVA, UPF (Low Power), Emulation, Formal Verification etc.

9.0

CourseMarks Score®

9.5

Freshness

9.4

Feedback

7.5

Content

Platform: Udemy
Video: 1h 10m
Language: English
Next start: On Demand

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