Functional Verification is one of the most time-consuming processes in ASIC design cycle; yet a structured introductory course/training/education on this topic is often missing. Neither the educational institutes offer this nor there are vendors offering such training. While several language specific courses are offered by EDA vendors, a comprehensive training on fundamentals of functional verification is lacking. This course gives you an in-depth introduction to the different aspects of functional verification including different testbench architectures. This course covers all aspects of functional verification ranging from verification architecture to building testbenches, gate level simulation and various technologies used in verification such as simulation, formal, emulation.
•To explore what is verification and why it is needed and how it is achieved.
•To examine the different testbench architectures available
•To suggest widely used guidelines and need for a methodology
•To elaborate on all the different terminologies, buzz words used in the industry
•To introduce different stages in functional verification such as RTL simulation, gate level simulation, emulation etc. and to address the challenges in each one of them
Table of Contents
Session 1: Introduction
•ASIC Design Flow
•A quick Verification 101
Session 2: Different Verification Technologies
Session 3: Metric Driven Verification (MDV)
•Assertion coverage (Control Centric)
•Functional Coverage (Data centric)
Session 4: Writing Testbenches
•What is a testbench anyway?
•HDL based – basic ones
Session 5: Coverage measurement in Verification
•What is coverage?
•Types of coverage
Session 6: Gate Level Simulation (GLS) & SDF annotation
•What is Gate Level Simulation
•SDF Annotation – typical timing violations
Session 7: Regressions – keeping the design stable
•Need for regressions
Session 8: Tips & tricks, Best Known Methods (BKMs)