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FPGAs Development with Xilinx Vivado tool & Pcie full project

In this course you will learn to develop FPGAs with VHDL language, FPGA is an integrated circuit - a chip that is making complex calculations in parallel an...
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9.9

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7.6

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9.2

Content

Platform: Skillshare
Video: 8h
Language: English
Next start: On Demand

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CourseMarks Score®

9.1 / 10

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9.9 / 10
This course was last updated on 9/2021.

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7.6 / 10
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Content Score

9.2 / 10
Video Score: 7.6 / 10
The course includes 8h video content. Courses with more videos usually have a higher average rating. We have found that the sweet spot is 16 hours of video, which is long enough to teach a topic comprehensively, but not overwhelming. Courses over 16 hours of video gets the maximum score.
The average video length is 7 hours 09 minutes of 15 VHDL courses on Udemy.
Detail Score: 10.0 / 10

The top online course contains a detailed description of the course, what you will learn and also a detailed description about the instructor.

Table of contents

Description

  • In this course you will learn to develop FPGAs with VHDL language, FPGA is an integrated circuit – a chip that is making complex calculations in parallel and can be program by the developer. today can be found in every smart phone, cars, plans, most of your electronics have FPGA.

  • Today, working as a FPGA developer is the most profitable job in Hardware development. And is a profession in great demand in every big company: apple, microsoft, intel, amazon, google and so many others!

  • If you want to work as a FPGA developer or just to know how to design an FPGA this is the course for you!

This Course was made for all levels by a professional electronic and computer engineer with a huge experience with FPGAs of all of the companies in the market. In this Course we will learn how to use Xilinx FPGAs tool –  Vivado design suite. I will use VIVADO 2019.1 but the course is valid for any version of VIVADO including 2020.

In this course you will learn everything you need to know for using Vivado design suite. Vivado design suite is a tool that was crated by Xilinx and is used to design Xilinx FPGAs, simulating them and real-time debugging them and of course to program them.

This course was created for beginners who never used Vivado before, and also for students who wants more experience with the Vivado design suite, also this course can help even advanced users for knowing and understanding how to use and design more complex parts in this tool – like Pcie, Axi interface, Simulations with 3rd party tool(Modelsim,Questasim…), Zynq7000 processor and much more.

This course will help the Students understand everything they needs to know for working in big companies with Vivado design suite as a professional designers/engineers.

In this course the students will learn how to simulate their project with Vivado and also with 3rd party tool – Modelsim. Students with no experience at Modelsim will learn briefly about Modelsim but i can guarantee that after the Full Project part in the course you will control the Modelsim which is a really easy tool to learn.

At the end of the course it includes a Full Project of 2.5 hours, with PCIE communication and simulating the PCIE Cores. This way after you have learned all of the parts of how to start your own project, you can also go and build a big project by using all of the aspects learned on this course.

I am willing to add more full projects with different complicated IP’s, so you will be able to use them as reference for your projects. my main goal is to make it easier for the students to be able to create any project they want.

The main topics this course will cover are:

  • How to download and install Vivado design suite 2019.1

  • How to download and install Modelsim

  • Create new project

  • Adding block design

  • Adding Xilinx IP cores

  • Xilinx Primitive Cores

  • Xilinx language templates

  • synthesize a project

  • Implementing the design

  • Creating Constraints

  • Generate Bitstream , Binstream and MCS files

  • Simulating the design through Vivado or Modelsim

  • Zynq 7000

  • Axi interfaces

  • Open SDK project

  • Real Time Integration with ILA – logic analyser

  • PCIE FULL Project with PCIE and Simulating the PCIE.

You will learn

PCIe Project:

In this project you will have to write a Root complex Pcie(The master) under the test bench that will be connected to the End Point Pcie(The slave), setup the Root complex and send data from the testbench to through the Master straight to the slave.

Main Steps:

  1.  Create a new project with top (see how to create a new project in lecture no.4)
  2.  Add an empty top Vhdl or Verilog file to your project (see how to add files to the project in lecture no.7)
  3. Add a new block design for the End Point and name it Pcie_block (see how to create block design at lecture no.8)
  4. Add 4 IP cores ,into the block design of PCIe_block. – the IP cores are “Axi Memory Mapped to pci express” + “processor system reset” +”Axi interconnect” + “amm slave bridge” (see how to add an ip core in lecture no.8)
  5. Connect between them and to the top (this step is hard, you might want to look at lecture 30+31)
  6. Connect a register file to the top (use the file attached here)
  7. Add a test bench vhdl or verilog file (see how to add the test bench file at Running and using Modelsim simulator at lecture no.22)
  8. Add to the top as a component to the testbench file ( you can use lecture no .32 to see how to do it)
  9. Create a block names “RP_block” under the testbench.
  10. add an ip to the RP_block , the ip will be “7 series integrated block for pci express”.
  11. change the RP block IP to be Root port
  12. Add another IP to the same RP_BLOCK , the ip will be “7 series integrated block for pci express” but make it End point ip.
  13. Open an example design of the end point IP (you can see lecture no.9)

from this part I recommend you to follow videos 30-33 of the PCIe and see how you did in this project and complete it with my guide there.

Go step by step and I can guarantee you will be able to run the PCIe communication between the test bench to the top and from there to the Register file.

Good Luck!

Requirements

There is no requirement, anyone can start this course.

This course is for

Anybody can take this course, as it is suitable for all levels.

How much does the FPGAs Development with Xilinx Vivado tool & Pcie full project course cost? Is it worth it?

You can enrol in this course with a Skillshare subscription that costs $8/month, but you start with a FREE 7-day trial. You can also enrol in thousands of courses on a variety of topics with your subscription, including several Vhdl courses.
The average price is $11.3 of 15 VHDL courses on Udemy.

Does the FPGAs Development with Xilinx Vivado tool & Pcie full project course have a money back guarantee or refund policy?

There is no money-back guarantee with Skillshare, but you can start with a free one-week trial to learn without risk. With the subscription, you can download classes to your tablet or phone using the Skillshare app.

Are there any SCHOLARSHIPS for this course?

At the moment we couldn't find any available scholarship forFPGAs Development with Xilinx Vivado tool & Pcie full project, but you can access more than 30 thousand classes for $8/month on Skillshare, including this one!

Who is the instructor? Is Ofer Keren a SCAM or a TRUSTED instructor?

Ofer Keren has created 5 courses that got 55 reviews which are generally positive. Ofer Keren has taught 3,394 students and received a 4.0 average review out of 55 reviews. Depending on the information available, Ofer Keren is a TRUSTED instructor.

9.1

CourseMarks Score®

9.9

Freshness

7.6

Feedback

9.2

Content

Platform: Skillshare
Video: 8h
Language: English
Next start: On Demand

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