Disclosure: when you buy through links on our site, we may earn an affiliate commission.

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Logic Design with Vitis-HLS
4.5
4.5/5
(209 reviews)
1,293 students
Created by

9.6

CourseMarks Score®

9.7

Freshness

9.0

Feedback

9.4

Content

Platform: Udemy
Video: 7h 47m
Language: English
Next start: On Demand

Table of contents

Description

This course is an elementary introduction to high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing combinational logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design, which quickly becomes a must-have skill for every hardware or software engineer who is keen on utilising FPGAs for their exceptional performance and low power consumption.
It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. This course is the first to build the HLS design flow and skills along with the digital logic circuit concepts from scratch. Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches.
This course is the first of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on combinational circuits. The other courses in the series will explain how to use HLS in designing sequential logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

You will learn

✓ Designing combinational logic circuits with C/C++ language using the HLS approach
✓ Understanding the basic concepts of High-Level Synthesis (HLS)
✓ Using HLS concepts for designing combinational logic circuits
✓ HLS design flow for FPGAs
✓ Working with Xilinx Vitis-HLS and Vivado suite Toolsets
✓ How to generate RTL hardware IPs using Vitis-HLS
✓ Writing C-testbench in HLS
✓ Implementing two exciting projects with HLS

Requirements

• Understanding the basic concepts of C/C++ coding
• Understanding the basic concepts of logic operators (e.g., AND, OR, XOR, SHIFT )
• BASYS3 evaluation board
• Xilinx Vitis-HLS and Vivado (download Vivado ML Edition, or Vivado Design Suite – HLx Editions for Windows or Linux)

This course is for

• Hardware engineers
• Software engineers who are interested in FPGAs
• Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
• Digital Logic enthusiasts
PhD
Mohammad Hosseinabady received the PhD degree in computer engineering. He has been teaching electronics and computer courses in several universities for more than ten years. He is currently working on high-level synthesis for FPGA. His goal is to make advanced reconfigurable technologies more accessible for everyone who may not have in-depth knowledge of FPGAs and the traditional hardware design methodologies. His research interests include high-level reliability and testability, reconfigurable architectures, dynamic resource management, and runtime power management. He has published several papers on these topics in IEE, IEEE and ACM transactions, journals and conference proceedings.

Browse all courses by on Coursemarks.
Platform: Udemy
Video: 7h 47m
Language: English
Next start: On Demand

Students are also interested in