Learn Clock Domain Crossing (CDC) design and verification concepts deeply by vlsideepdive.
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Industry Expert: Vikas Sachdeva (Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. Vikas manages everything related to CDC products at Real Intent. He has multiple published papers and 2 patents in CDC. )
The course covers the following topics in CDC
•Synchronous and Asynchronous Clocks
•Metastability
•Synchronizers
•MTBF
•Effects of Metastability
•Glitch on Synchronizers
•Pulse Width on Synchronizers
•Open and Closed Loop synchronizers
•Passing multiple signals across clock domains
•Counters
•Data path synchronization
•FIFOs
•Reset Paths
•CDC Verifications steps
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Courses » Design » Design Tools » VLSI » Clock Domain Crossing Design & Verification (CDC)
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Clock Domain Crossing Design & Verification (CDC)
The course covers all basic concepts in CDC design and verification
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This course contains:
Table of contents
Description
You will learn
✓ Understand how to avoid metastability in presence of Asynchronous clocks
✓ Understand how avoid correlation loss across synchronizers
✓ Understand design of FIFOs
Requirements
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Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. He was worked in design, development and deployment of multiple static and constraints products.
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